One prior art application of arithmetic logic units which perform single-word and double-word operations is a data processor using single-word length data words and double-word length memory address. In one step, such a data processor performs an arithmetical logic operation, such as addition, by adding two registers together and storing the result in one of the registers. The processor performs memory address calculations in two steps using address information stored in pairs of registers. If the address calculation involves adding two addresses together, the first step requires the registers in each pair which contain the least significant address bits be added together and the result be stored into one of the registers. The second step requires the registers of each pair which contain the most significant address bits be added together and the result be stored into one of the registers. The resulting address from the calculation is not available for accessing a memory unit until the second calculation has been performed.
U.S. Pat. No. 3,660,646 teaches a method for error detection which is simply to do the calculations twice and compare the stored data results. However, this error detection approach suffers from the problem that the address is not available for accessing the memory until after two calculations, and the same arithmetic unit is used to check itself. Another error detection method known in the prior art is to fully duplicate the registers and arithmetic unit in the processor and to do the two address calculations in parallel with respect to both sets of registers and ALUs. This approach doubles the amount of circuitry required.